1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system including a memory controller for controlling the memory device.
2. Description of the Related Art
As semiconductor-related technology advances, the operation speed of semiconductor memory devices increases. An example of semiconductor memory devices is a Synchronous Dynamic Random Access Memory (SDRAM), which operates in synchronization with an external clock. SDRAM may use a Double Data Rate scheme to increase a data transfer rate by inputting/outputting data in synchronization with not only a rising edge of a clock but also a falling edge of the clock as well. This DDR SDRAM technology used in DDR2 and DDR3 schemes is an improvement over a DDR1 scheme. In case of DDR1, a two-bit prefetch is performed and an input/output data has a burst length (BL) of 2, and in case of DDR2, a 4-bit prefetch is performed and an input/output data has a burst length (BL) of 4. In case of DDR3, an 8-bit prefetch is performed and an input/output data has a burst length (BL) of 8. Here, the burst length (BL) of an input/output data being 8 indicates that 8-bit data which is synchronized with a clock are consecutively inputted/outputted through one data input/output pad.
When a memory device performs a read operation of receiving a read command and outputting a stored data in response to the read command, it takes some time for the data stored in a memory cell region to be outputted to outside the memory device through an internal circuit. Thus, read commands applied from outside is to be applied with a minimum time interval, which is a CAS to CAS delay time (tCCD). For example, when a DDR3 SDRAM performs a read operation with a burst length of 8 (BL8), the time interval between the read commands that are applied consecutively may be at least 4tCK.
FIG. 1 is a block view illustrating a data output path of a conventional memory device. Here, it is assumed that the memory device is a DDR3 SDRAM device.
Referring to FIG. 1, the conventional memory device includes a memory cell region 101, global data buses GIO<0:7>, a data transfer unit 103, a parallel-to-serial converter 105, and a data output pad 107. Here, FIG. 1 illustrates a structure between the memory cell region 101 and a data output pad 107, where a memory device may have a number of such structures equal to a number of data output pads.
When a read command is applied to the memory device, multi-bit parallel data stored in the memory cell region 101 are transferred to the data transfer unit 103 through the global data buses GIO<0:7>. The data transfer unit 103 receiving the transferred data latches the transferred parallel data and when an output signal PIN is enabled, transfers the latched data to the parallel-to-serial converter 105 through DOUTP<0:7>. The parallel-to-serial converter 105 converts the received parallel data into serial data and outputs the serial data through the data output pad 107.
The DDR3 SDRAM device is designed to perform a burst length 8 (BL8) operation, but it may support a BL4 operation as well. Hereafter, the DDR3 SDRAM is described with reference to FIGS. 2A and 2B.
FIG. 2A is an operation timing diagram of a burst length 8 (BL8) read operation of the memory device shown in FIG. 1.
Here, a timing when a read command is applied and a timing when data are outputted to the global data buses GIO<0:7> corresponding to the read command application moment are shown to be the same for illustration purposes. In an actual environment, a read command is applied first, and after a time equal to a CAS latency elapses, the data corresponding to the read command are outputted.
Referring to FIG. 2A, when the DDR3 SDRAM device performs a BL8 read operation, read commands RD1 and RD2 are applied at an interval of 4 tCK, and 8-bit parallel data D0 to D7 and D8 to D15 which respectively correspond to the read commands RD1 and RD2 are outputted from the memory cell region 101 and transferred to the data transfer unit 103 through the global data buses GIO<0:7>. The data transfer unit 103 latches the received 8-bit parallel data D0 to D7 and D8 to D15 and transfers the latched data to the DOUTP<0:7> at a timing when the output signal PIN is enabled to a logic high level. The output signal PIN is enabled at the interval of 4 tCK. The parallel-to-serial converter 105 converts the 8-bit parallel data D0 to D7 and D8 to D15, which are transferred at every 4 tCK, into serial data, and the serial data D0, D1, . . . , D7/D8, D9, . . . , D15 are outputted to outside the memory device through the data output pad 107.
FIG. 2B is an operation timing diagram of a burst length 4 (BL4) read operation of the memory device shown in FIG. 1.
Referring to FIG. 2B, when the DDR3 SDRAM device performs a BL4 read operation, 4-bit parallel data D0 to D3 and D4 to D7 which respectively correspond to the read commands RD1 and RD2 are outputted from the memory cell region 101 and transferred to the data transfer unit 103 through the global data buses GIO<0:7>. The data transfer unit 103 latches the received 4-bit parallel data D0 to D3 and D4 to D7 and transfers the latched data to the DOUTP<0:7> at a timing when the output signal PIN is enabled to a logic high level. Here, according to an example, only four lines of the global data buses GIO<0:7> and only four lines of the DOUTP<0:7> may be used. The output signal PIN is enabled at the interval of 4 tCK. The parallel-to-serial converter 105 converts the 8-bit parallel data D0 to D3 and D4 to D7, which are transferred at every 4 tCK, into serial data, and the serial data D0, D1, D2, D3/D4, D5, D6, D7 are outputted to outside the memory device through the data output pad 107.
Here, to obtain the same data output efficiency of the BL8 operation during the BL4 operation, the read commands RD1 and RD2 may be applied at half the interval used for the BL8 (that is, 2 tCK). However, a minimum time to physically read and transfer read the data recorded in a memory cell through the global data buses GIO<0:7>, which may have significant parasitic capacitance and parasitic resistance, may be longer (for example, 4 tCK) than 2 tCK. When the minimum time to physically read and transfer data recorded in a memory cell equals 4tCK, the read commands RD1 and RD2 are to be applied with a time interval of at least tCCD, which is 4 tCK, during the BL4 operation.
Here, since the consecutive read commands RD1 and RD2 are to be applied at the interval of 4 tCK during the BL4 operation of the conventional memory device as in the BL8 operation, data is not output for 2 tCK period of each 4 tCK interval in the memory device. Therefore, the data transfer efficiency is decreased by half as compared with the BL8 operation.